(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal silicon oxide field effect transistor, (MOSFET), device, featuring a self-aligned contact, (SAC), structure.
(2) Description of Prior Art
Static random access memory, (SRAM), cells are usually comprised of six MOSFET devices, preferably four NFET, (n channel), devices, and two PFET, (p channel), devices. In general, to decrease the cost of semiconductor chips, the cell size, or SRAM cells in this case, have to be decreased, to allow a greater amount of smaller semiconductor chips to be obtained from a specific size starting substrate, thus reducing the processing cost of each specific semiconductor chip, however with the now smaller SRAM cell, still supplying the device density and performance obtained with SRAM cells fabricated with larger features. Therefore to decrease SRAM cell size, the size of the PFET and NFET devices have to be reduced.
Micro-miniaturization, or the use of sub-micron features, obtained via optimization of specific fabrication disciplines, such as photolithography, and dry etching, have allowed the objective of smaller MOSFET devices, to be partially realized. However the use of specific design and structural innovations, such as a self-aligned opening, and a self-aligned contact, structure, have also contributed to the attainment of smaller SRAM devices, and cells, resulting in smaller, less expensive, SRAM semiconductor chips. When using conventional, or non-SAC hole opening procedures, to expose an underlying active device region, in a semiconductor substrate, the area of the active device region has to be increased to insure that this opening is fully landed on this region. This results in an increase in the designed dimension of the active device region, resulting in larger than desired cells, or chips. The SAC procedure however, as applied to an active device region such as a source/drain region, is comprised of an opening larger in diameter than the space between gate structures, where a source/drain region is located. This is accomplished via selective reactive ion etching, (RIE), procedures allowing the SAC opening to expose a portion of the top surface of insulator capped, gate structures, as well as the active device region, located between the insulator capped gate structures.
This invention will describe a procedure in which a SAC opening is made to a small designed space between insulator capped gate structures, with composite spacers on the sides of the gate structures. After definition of an active device region, such as a source/drain region, the space is enlarged via the removal of a component of the composite spacer. This process sequence allows the amount of designed active device area, needed to accommodate the SAC opening, to be reduced, however still allowing the needed amount of contact area when filled with an overlying SAC structure, due to the removal of a component of the composite spacer. Prior art, relating to SAC procedures, such as Chou et al, in U.S. Pat. No. 5,731,236, describe a SAC structure, however without the novel re-etched, or removed, spacer component, used in the present invention to increase device density.